Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
As the performance of electronic systems employing flash memory devices increases, flash memory device performance should also increase. A performance increase includes reducing power consumption, increasing speed, and increasing the memory density. One way to accomplish these tasks is by decreasing the size of each memory cell.
Unfortunately, there are resulting problems with decreasing the memory cell size. One such problem is that, as the channel length and gate oxide thickness are reduced, leakage current increases. One type of leakage current is gate induced drain leakage (GIDL) that results due to the depletion at the drain surface below the gate-drain overlap region.
GIDL can cause a problem referred to as program disturb during a programming operation. For example, FIG. 1 illustrates a portion of a typical prior art NAND flash memory array. During a program operation to program a memory cell 101, the wordline 102 coupled to that cell 101 is biased with a 20V programming pulse. The bitline 106 coupled to that cell is brought to ground potential. This provides a gate to source potential of 20V across the cell 101 to be programmed.
The other cells on the selected wordline 102 will also have the 20V programming pulse applied. In order to inhibit these cells from being programmed, their bitlines 105 are biased to VCC. Additionally, the remaining unselected wordlines are biased with 10V pulses. This biasing creates a channel voltage of approximately 7V on the unselected cell 103. This provides a gate to source voltage of approximately 13V that is below the required programming voltage.
Since the source select gate line is at 0V in order to turn off those select transistors, there is a voltage drop of 7V from drain to gate 110 that can cause the 7V on the unselected cell to leak away, thus creating the possibility that the unselected cell 103 is programmed. This is referred to in the art as program disturb.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to reduce program disturb in a memory device.